Research
This page contains some information regarding the research I am performing and have performed in the past. Some undergraduate projects are also inculded
Ph.D. Thesis
Challenges in Nanometre Digital Integrated Circuit Design
Technology trends, driven by the desire for higher transistor densities and faster de vices, have led to transistor dimensions scaling into the nanometre regime. However, with this continued scaling, digital Integrated Circuits (ICs) have faced many challenges that include: increased leakage power dissipation, increased process variations of transistor parameters and increased sensitivity of ICs to the surrounding electromagnetic radiation. These challenges are having a significant effect on circuit performance and power, making it more diffcult to design circuits that achieve a required specifcation. This thesis presents new techniques for addressing these challenges in digital circuits.
First, a new Static Random Access Memory (SRAM) cell is presented that reduces gate leakage power in caches while maintaining low access latency and stability. The new cell design, compared to a conventional SRAM cell, has one additional transistor and exploits the strong bias towards logic-0 at the bit level exhibited by the memory value stream of ordinary programs. Then, techniques for reducing leakage power in Field-Programmable-Gate-Array (FPGA) routing switches and look-up tables are pre- sented; the new circuits significantly reduce the leakage power in those circuits with varying amounts of area and/or performance cost.
Next, circuit and architectural techniques that reduce the Soft-Error-Rate (SER) in a Content-Addressable Memory (CAM) are presented; the first technique augments a Ternary-CAM cell with extra transistors to make it more immune to soft errors, and the second technique, applicable to Binary-CAM cells, adds parity bits to each CAM word and then modifies the sensing scheme so that both a match and a one-bit miss constitute a successful search. The main cost of both of these schemes is increased area.
Then a scheme to compensate for Within-Die (WID) variations in domino logic is presented; the new technique reduces the variation in leakage, delay and noise margin with a small area overhead. Finally a new methodology which takes into consideration the effect of WID process variations on a low-voltage parallel system is presented. The new methodology shows that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel system.
My supervisor for my thesis is Professor Farid Najm.
Master's Thesis
Low Leakage Asymmetric-Cell SRAM
My Thesis for my Master's Degree is the design of an asymmetrical low leakage SRAM cell for caches. The following is the abstract of the thesis
In this work a novel family of asymmetric dual-Vt SRAM cell designs that reduce leakage power in caches while maintaining low access latency is introduced. The asymmetrical cell family is built on the following premise: select a preferred stored value and weaken, by increasing the threshold voltage, only those transistors necessary to drastically reduce leakage when this value is stored. The designs exploit the strong bias towards zero at the bit level exhibited by the memory values of ordinary programs. Relative to conventional symmetric high-performance cells, the asymmetric cells offer significant leakage reduction in the zero state and in some cases also in the one state albeit to a lesser extent. A unique sense-amplifier, in combination with dummy bitlines, enables read times to be comparable to conventional symmetric cells. With one cell design, leakage is reduced by 7 times (in the zero state) with no performance degradation, but with a stability degradation of 6%. Another cell design reduces leakage by 2 times (in the zero state) with no performance or stability loss. An alternative cell design reduces leakage by 58 times (in the zero state) with a performance degradation of 1% and an area increase of 2% and no stability degradation.
PDF Copy of Thesis
PS Copy of Thesis
My supervisors for my Master's were Professor Farid Najm and Professor Andreas Moshovos.
Undergraduate Thesis
Parametrized Processor Design Tool
Borys Bradel, Tomasz Czajkowski, Michael Krejcik. and I developed a program that created a parameterized processor for implementation in an FPGA. There was a graphical interface that allowed a user to specify the types of instructions that the processor should provide (basic ones like move, and optional ones like multiply) and then a CAD tool created the processor by automatically generating VHDL code that described the processor as well as the assembler for the processor.
We were supervised by Professor Steven Brown.
Computer Organization Project
Wheely Bug
This project created an autonomous robot. I worked with Babak Vaez.
The robot, made out of lego, was controlled by a Motorola 68000 assemby program. The robots program instructed the robot to search for food and then bring it back home. During this time it remained within its field.
Algorithms Project
Connect 4 Aritificial Player
The creation of a Connect 4 playing artificial intelligence
